This course provides an overview of the design process of a large design in modern integrated circuit at the 65nm, 45nm, and 28nm node (depending on the availability of the corresponding design kit). A custom dual-port SRAM block, which can be embedded into an FPGA or other integrated circuit, is used as a design example throughout the course.

Via the SRAM example, this course will focus on 1) the required tasks to design a robust circuit in a modern CMOS process, and 2) aspects of leading analysis and die cost estimation, behavioural modeling, logic verification, mixed-signal simulation, and task management of large designs.