This course presents theory and practice for the synthesis of digital systems at the behavioural level (algorithm level), register transfer level and logic level.

Lecture topics focus on classic subjects such as micro-architecture, control/data flow analysis, optimization, scheduling, resource and interconnect binding, multi-level logic synthesis, technology mapping and retiming. Lecture topics also extend to cover advanced frontend issues, such as the synthesis of object oriented language constructs, as well as advanced backend issues, such as the interaction with layout design.

The class project involves the construction of a complete behavioral synthesis tool from C to synthesizable HDL.